A conventional burn-in test of an IC chip employs a method of packaging the IC, inserting the packaged IC in a socket disposed on a printed circuit board and testing while applying a load voltage at a high temperature, but the need for an unpackaged IC chip, which has already been subjected to a burn-in test and an electric test, has increased for a chip on a board or a multichip module, and development of such has progressed rapidly in recent times.
In particular, testing of an IC before dicing has many advantages; for example, the cost for the test is decreased, the testing apparatus is small-sized, the testing time is shortened, the yield of ICs is improved since the cause of a defect(s) during the production of the IC is identified and can be corrected, the shipment is rationalized, etc.
A so-called probe card having bumps for connecting an electrically conductive circuit and IC pads to an insulating holder having a flexibility has recently been developed to conduct the electric test in a die level, as disclosed in, for example, JP-A-62-182672 (the term "JP-A", as used herein, means an "unexamined published Japanese patent application"), but the probe card is for the test in a die level.
To test all ICs on a wafer at the same time in a wafer scale, it is necessary to make the wiring very close or employ a multilayer wiring structure.
However, if the multilayer wiring structure is employed to increase the wiring density, the flexibility of the probe card is lost, whereby it is impossible to absorb the variation of the height of the IC pads, and a good connection between the bump of the probe card and the IC pads cannot be obtained.
Even if monolayer wiring can be attained using a high density wiring board, where an organic polymeric material having a flexibility, such as polyimide, an epoxy resin, polyether imide, polysulfone, benzocylcobutene, etc., is used as a substrate material, since a coefficient of thermal expansion of the organic polymeric material greatly differs from that of silicon (which is the material of the wafer), and, hence, there is the problem that when a burn-in test is conducted, a positional shift between the bump and the IC pad occurs due to the difference in the dimensional change at high temperatures (about 150.degree. C.), a good connection is not obtained.
Further, where an inorganic material having substantially the same coefficient of thermal expansion as that of a silicon wafer, such as a silicon substrate, a ceramic substrate, a glass substrate, a metal substrate, etc., is used, there is a problem in flexibility and it is difficult to obtain a sure connection.